Friday, 22 July 2005
A.Farina,
L.Tronchin
50/86
Convolution
(2):
y:=0;
FOR n:=0 TO N-1 DO
y:=
y + a[n]·x[n];
Multiply and ACcumulate
On a DSP board this instruction is
performed in one cycle
• Clock core = 100 MHz
• Sample frequency fS = 48 KHz
Þ
Upper limit is 2000 MAC per sample