Implementation of a double StereoDipole system on a DSP board – Eperimental validation and subjective evaluation inside a car cockpit

20 October 2003

WASPAA 2003 - New Paltz, NY

Convolution (2):

Industrial Engineering Dept.

University of Parma – Italy

y:=0;

FOR n:=0 TO N-1 DO

y:= y + a[n]·x[n];

Multiply and ACcumulate

On a DSP board this instruction is performed in one cycle

• Clock core = 100 MHz

• Sample frequency fS = 48 KHz

Upper limit is 2000 MAC per sample